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general description the MAX1196 is a 3v, dual 8-bit analog-to-digital con- verter (adc) featuring fully differential wideband track- and-hold (t/h) inputs, driving two adcs. the MAX1196 is optimized for low power, small size, and high-dynamic performance for applications in imaging, instrumenta- tion, and digital communications. this adc operates from a single 2.7v to 3.6v supply, consuming only 87mw while delivering a typical signal-to-noise and dis- tortion (sinad) of 48.4db at an input frequency of 20mhz and a sampling rate of 40msps. the t/h driven input stages incorporate 400mhz (-3db) input ampli- fiers. the converters can also be operated with single- ended inputs. in addition to low operating power, the MAX1196 features a 3ma sleep mode as well as a 0.1? power-down mode to conserve power during idle periods. an internal 2.048v precision bandgap reference sets the full-scale range of the adc. a flexible reference structure allows the use of this internal or an externally applied reference, if desired for applications requiring increased accuracy or a different input voltage range. the MAX1196 features parallel, multiplexed, cmos- compatible three-state outputs. the digital output format can be set to two? complement or straight offset binary through a single control pin. the device provides for a separate output power supply of 1.7v to 3.6v for flexible interfacing. the MAX1196 is available in a 7mm 7mm, 48-pin tqfp package, and is specified for the extended industrial (-40? to +85?) temperature range. pin-compatible, nonmultiplexed higher speed versions of the MAX1196 are also available. refer to the max1198 data sheet for 100msps, the max1197 data sheet for 60msps, and the max1195 data sheet for 40msps. for a 10-bit, pin-compatible upgrade, refer to the max1186 data sheet. with the n.c. pins of the MAX1196 internally pulled down to ground, this adc becomes a drop-in replacement for the max1186. applications baseband i/q sampling multichannel if sampling ultrasound and medical imaging battery-powered instrumentation wlan, wwan, wll, mmds modems set-top boxes vsat terminals features single 2.7v to 3.6v operation excellent dynamic performance 48.4db/44.7db sinad at f in = 20mhz/200mhz 68.9db/53dbc sfdr at f in = 20mhz/200mhz -72db interchannel crosstalk at f in = 20mhz low power 87mw (normal operation) 9mw (sleep mode) 0.3? (shutdown mode) 0.05db gain and 0.05 phase matching wide 1v p-p differential analog input voltage range 400mhz -3db input bandwidth on-chip 2.048v precision bandgap reference user-selectable output format?wo? complement or offset binary pin-compatible 8-bit and 10-bit upgrades available MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs ________________________________________________________________ maxim integrated products 1 n.c. n.c. ognd ov dd ov dd ognd a/b n.c. n.c. n.c. n.c. n.c. com v dd gnd ina+ ina- v dd gnd inb- inb+ gnd v dd clk 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 tqfp-ep MAX1196 gnd v dd v dd gnd t/b sleep pd oe n.c. n.c. n.c. n.c. 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 refn refp refin refout d7a/b d6a/b d5a/b d4a/b d3a/b d2a/b d1a/b d0a/b part temp range pin-package MAX1196ecm -40 c to +85 c 48 tqfp-ep* pin configuration ordering information 19-2600; rev 0; 9/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * ep = exposed pad. functional diagram appears at end of data sheet.
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = ov dd = 3v, 0.1f and 2.2f capacitors from refp, refn, and com to gnd; refout connected to refin through a 10k ? resistor, v in = 2v p-p (differential with respect to com), c l = 10pf at digital outputs (note 5), f clk = 40mhz, t a = t min to t max , unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and characterization. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd , ov dd to gnd .............................................. -0.3v to +3.6v ognd to gnd...................................................... -0.3v to +0.3v ina+, ina-, inb+, inb- to gnd ...............................-0.3v to v dd refin, refout, refp, refn, com, clk to gnd............................................-0.3v to (v dd + 0.3v) oe , pd, sleep, t/b, d7a/b d0a/b, a/b to ognd...............-0.3v to (ov dd + 0.3v) continuous power dissipation (t a = +70 c) 48-pin tqfp (derate 12.5mw/ c above +70 c)........1000mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-60 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units dc accuracy resolution 8 bits integral nonlinearity inl f in = 7.51mhz (note 1) 0.3 1 lsb differential nonlinearity dnl f in = 7.51mhz, no missing codes guaranteed (note 1) 0.15 1 lsb offset error 4 %fs gain error 4 %fs gain temperature coefficient 100 ppm/ c analog input differential input voltage range v diff differential or single-ended inputs 1.0 v common-mode input voltage range v cm v dd / 2 0.2 v input resistance r in switched capacitor load 140 k ? input capacitance c in 5pf conversion rate maximum clock frequency f clk 40 mhz cha 5 data latency chb 5.5 clock cycles dynamic characteristics (f clk = 40mhz) f ina or b = 2mhz at -1db fs 48.7 f ina or b = 7.5mhz at -1db fs 48.7 f ina or b = 20mhz at -1db fs 47.5 48.5 signal-to-noise ratio snr f ina or b = 101mhz at -1db fs 48 db f ina or b = 2mhz at -1db fs 48.6 f ina or b = 7.5mhz at -1db fs 48.7 f ina or b = 20mhz at -1db fs 47 48.4 signal-to-noise and distortion sinad f ina or b = 101mhz at -1db fs 48 db
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = ov dd = 3v, 0.1f and 2.2f capacitors from refp, refn, and com to gnd; refout connected to refin through a 10k ? resistor, v in = 2v p-p (differential with respect to com), c l = 10pf at digital outputs (note 5), f clk = 40mhz, t a = t min to t max , unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units f ina or b = 2mhz at -1db fs 69 f ina or b = 7.5mhz at -1db fs 70 f ina or b = 20mhz at -1db fs 60 68.9 spurious-free dynamic range sfdr f ina or b = 101mhz at -1db fs 65 dbc f ina or b = 2mhz at -1db fs -72 f ina or b = 7.5mhz at -1db fs -73.7 f ina or b = 20mhz at -1db fs -75 third-harmonic distortion hd3 f ina or b = 101mhz at -1db fs -67 dbc f in1(a or b) = 1.997mhz at -7db fs, intermodulation distortion ( fir st fi ve od d- or der im d s) ( n ote 2) imd f in2(a or b) = 2.046mhz at -7db fs -68 dbc f in1(a or b) = 1.997mhz at -7db fs, third-order intermodulation distortion (note 2) im3 f in2(a or b) = 2.046mhz at -7db fs -73.2 dbc f ina or b = 2mhz at -1db fs -70 f ina or b = 7.5mhz at -1db fs -69 f ina or b = 20mhz at -1db fs -69 -57 total harmonic distortion (first four harmonics) thd f ina or b = 101mhz at -1db fs -63 dbc small-signal bandwidth input at -20db fs, differential inputs 500 mhz full-power bandwidth fpbw input at -1db fs, differential inputs 400 mhz f in1(a or b) = 106mhz at -1db fs, gain flatness (12mhz spacing) (note 3) f in2(a or b) = 118mhz at -1db fs 0.05 db aperture delay t ad 1ns aperture jitter t aj 1db snr degradation at nyquist 2 ps rms overdrive recovery time for 1.5 full-scale input 2 ns internal reference (refin = refout through 10k ? resistor; refp, refn, and com levels are generated internally.) reference output voltage v refout (note 4) 2.048 3% v positive reference output voltage v refp (note 5) 2.012 v negative reference output voltage v refn (note 5) 0.988 v common-mode level v com (note 5) v dd / 2 0.1 v differential reference output voltage range ? v ref ? v ref = v refp - v refn 1.024 3% v reference temperature coefficient tc ref 100 ppm/ c
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = ov dd = 3v, 0.1f and 2.2f capacitors from refp, refn, and com to gnd; refout connected to refin through a 10k ? resistor, v in = 2v p-p (differential with respect to com), c l = 10pf at digital outputs (note 5), f clk = 40mhz, t a = t min to t max , unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units buffered external reference (v refin = 2.048v) positive reference output voltage v refp (note 5) 2.012 v negative reference output voltage v refn (note 5) 0.988 v common-mode level v com (note 5) v dd / 2 0.1 v differential reference output voltage range ? v ref ? v ref = v refp - v refn 1.024 2% v refin resistance r refin >50 m ? maximum refp, com source current i source 5ma maximum refp, c om s i nk c ur r ent i sink -250 a maximum refn source current i source 250 a maximum refn sink current i sink -5 ma unbuffered external reference (v refin = agnd, reference voltage applied to refp, refn, and com) refp, refn input resistance r refp , r refn measured between refp and refn 4 k ? refp, refn, com input capacitance c in 15 pf differential reference input voltage range ? v ref ? v ref = v refp - v refn 1.024 10% v com input voltage range v com v dd / 2 5% v refp input voltage v refp v c om + ? v re f / 2 v refn input voltage v refn v com - ? v ref / 2 v digital inputs (clk, pd, oe , sleep, t/b) clk 0.8 v dd input high threshold v ih pd, oe , sleep, t/b 0.8 oe , sleep, t/b 0.2
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs _______________________________________________________________________________________ 5 electrical characteristics (continued) (v dd = ov dd = 3v, 0.1f and 2.2f capacitors from refp, refn, and com to gnd; refout connected to refin through a 10k ? resistor, v in = 2v p-p (differential with respect to com), c l = 10pf at digital outputs (note 5), f clk = 40mhz, t a = t min to t max , unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units input hysteresis v hyst 0.15 v i ih v ih = v dd = ov dd 20 input leakage i il v il = 0 20 a input capacitance c in 5pf digital outputs (d0a/b d7a/b, a/b) output voltage low v ol i sink = -200a 0.2 v output voltage high v oh i source = 200a ov dd - 0.2 v three-state leakage current i leak oe = ov dd 10 a three-state output capacitance c out oe = ov dd 5pf power requirements analog supply voltage range v dd 2.7 3 3.6 v output supply voltage range ov dd 1.7 3 3.6 v operating, f ina&b = 20mhz at -1db fs applied to both channels 29 36 sleep mode 3 ma analog supply current i vdd shutdown, clock idle, pd = oe = ov dd 0.1 20 a operating, f ina&b = 20mhz at -1db fs applied to both channels (note 6) 8ma sleep mode 3 output supply current i ovdd shutdown, clock idle, pd = oe = ov dd 310 a operating, f ina&b = 20mhz at -1db fs applied to both channels 87 108 sleep mode 9 mw analog power dissipation pdiss shutdown, clock idle, pd = oe = ov dd 0.3 60 w offset, v dd 5% 3 power-supply rejection psrr gain, v dd 5% 3 mv/v timing characteristics clk rise to cha output data valid t doa c l = 20pf (notes 1, 7) 6 8.25 ns clk fall to chb output data valid t dob c l = 20pf (notes 1, 7) 6 8.25 ns clock rise/fall to a/b rise/fall time t da/b 6ns oe fall to output enable time t enable 5ns oe rise to output disable time t disable 5ns clk pulse width high t ch clock period: 25ns (note 7) 12.5 1.5 ns
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs 6 _______________________________________________________________________________________ note 1: guaranteed by design. not subject to production testing. note 2: intermodulation distortion is the total power of the intermodulation products relative to the total input power. note 3: analog attenuation is defined as the amount of attenuation of the fundamental bin from a converted fft between two applied input signals with the same magnitude (peak-to-peak) at f in1 and f in2 . note 4: refin and refout should be bypassed to gnd with a 0.1f (min) and 2.2f (typ) capacitor. note 5: refp, refn, and com should be bypassed to gnd with a 0.1f (min) and 2.2f (typ) capacitor. note 6: typical digital output current at f ina&b = 20mhz. for digital output currents vs. analog input frequency, see the typical operating characteristics. note 7: see figure 3 for detailed system timing diagrams. clock to data valid timing is measured from 50% of the clock level to 50% of the data output level. note 8: sinad settles to within 0.5db of its typical value in unbuffered external reference mode. note 9: crosstalk rejection is tested by applying a test tone to one channel and holding the other channel at dc level. crosstalk is measured by calculating the power ratio of the fundamental of each channel s fft. note 10: amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda- mental of the calculated fft. note 11: phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of the calculated fft. the data from both adc channels must be captured simultaneously during this test. electrical characteristics (continued) (v dd = ov dd = 3v, 0.1f and 2.2f capacitors from refp, refn, and com to gnd; refout connected to refin through a 10k ? resistor, v in = 2v p-p (differential with respect to com), c l = 10pf at digital outputs (note 5), f clk = 40mhz, t a = t min to t max , unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units clk pulse width low t cl clock period: 25ns (note 7) 12.5 1.5 ns wake-up from sleep mode 1 wake-up time t wake wake-up from shutdown mode (note 8) 20 s channel-to-channel matching crosstalk f ina or b = 20mhz at -1db fs (note 9) -72 db gain matching f ina or b = 20mhz at -1db fs (note 10) 0.05 db phase matching f ina or b = 20mhz at -1db fs (note 11) 0.05 d eg r ees
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs _______________________________________________________________________________________ 7 typical operating characteristics (v dd = ov dd = 3v, v refin = 2.048v, differential input at -1db fs, f clk = 40mhz, c l 10pf, t a = +25 c, unless otherwise noted.) fft plot cha (differential input, 8192-point data record) MAX1196-01 analog input frequency (mhz) amplitude (db) 18 16 12 14 4 6 8 10 2 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 020 f ina f clk = 40.0005678mhz f ina = 1.958036mhz f inb = 7.534287mhz aina = ainb = -1db fs coherent sampling f inb hd2 hd3 fft plot chb (differential input, 8192-point data record) MAX1196-02 analog input frequency (mhz) amplitude (db) 18 16 12 14 4 6 8 10 2 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 020 f ina f clk = 40.0005678mhz f ina = 1.958036mhz f inb = 7.534287mhz aina = ainb = -1db fs coherent sampling f inb hd2 hd3 fft plot cha (differential input, 8192-point data record) MAX1196-03 analog input frequency (mhz) amplitude (db) 18 16 12 14 4 6 8 10 2 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 020 f ina f clk = 40.0005678mhz f ina = 7.534287mhz f inb = 1.958036mhz aina = ainb = -1db fs coherent sampling f inb hd2 hd3 fft plot chb (differential input, 8192-point data record) MAX1196-04 analog input frequency (mhz) amplitude (db) 18 16 12 14 4 6 8 10 2 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 020 f ina f clk = 40.0005678mhz f ina = 7.534287mhz f inb = 1.958036mhz aina = ainb = -1db fs coherent sampling f inb hd2 hd3 fft plot cha (differential input, 8192-point data record) MAX1196-05 analog input frequency (mhz) amplitude (db) 18 16 12 14 4 6 8 10 2 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 020 f ina f clk = 40.0005678mhz f ina = 19.88798mhz f inb = 40.49374mhz aina = ainb = -1db fs coherent sampling f inb hd2 hd3 fft plot chb (differential input, 8192-point data record) MAX1196-06 analog input frequency (mhz) amplitude (db) 18 16 12 14 4 6 8 10 2 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 020 f ina f clk = 40.0005678mhz f ina = 19.88798mhz f inb = 40.49374mhz aina = ainb = -1db fs coherent sampling f inb hd2 hd3 fft plot cha (differential input, 8192-point data record) MAX1196-07 analog input frequency (mhz) amplitude (db) 18 16 12 14 4 6 8 10 2 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 020 f ina f clk = 40.0005678mhz f ina = 40.49374mhz f inb = 19.88798mhz aina = ainb = -1db fs coherent sampling f inb hd2 hd3 fft plot chb (differential input, 8192-point data record) MAX1196-08 analog input frequency (mhz) amplitude (db) 18 16 12 14 4 6 8 10 2 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 020 f ina f clk = 40.0005678mhz f ina = 40.49374mhz f inb = 19.88798mhz aina = ainb = -1db fs coherent sampling f inb hd2 hd3 two-tone imd plot (differential input, 8192-point data record) MAX1196-09 analog input frequency (mhz) amplitude (db) 4.5 4.0 3.0 3.5 1.5 2.0 2.5 1.0 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 0.5 5.0 f clk = 40.001536mhz f ina = 1.997147mhz f inb = 2.045977mhz ain = -7db fs coherent sampling f in2 f in1
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs 8 _______________________________________________________________________________________ typical operating characteristics (continued) (v dd = ov dd = 3v, v refin = 2.048v, differential input at -1db fs, f clk = 40mhz, c l 10pf, t a = +25 c, unless otherwise noted.) two-tone imd plot (differential input, 8192-point data record) MAX1196-10 analog input frequency (mhz) amplitude (db) 12 11 10 9 8 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 713 f clk = 40.001536mhz f in1 = 9.95643mhz f in2 = 10.024799mhz ain = -7db fs coherent sampling f in1 f in2 signal-to-noise ratio vs. analog input frequency MAX1196-11 analog input frequency (mhz) snr (db) 160 120 80 40 45 46 47 48 49 50 44 0 200 cha chb signal-to-noise + distortion vs. analog input frequency MAX1196-12 analog input frequency (mhz) sinad (db) 160 120 80 40 44 45 46 47 48 49 50 43 0 200 cha chb total harmonic distortion vs. analog input frequency MAX1196-13 analog input frequency (mhz) thd (dbc) 160 120 80 40 -78 -68 -58 -48 -38 -88 0 200 chb cha spurious-free dynamic range vs. analog input frequency MAX1196-14 analog input frequency (mhz) sfdr (dbc) 160 120 80 40 50 60 70 80 90 40 0 200 cha chb 1 10 100 1000 full-power input bandwidth vs. analog input frequency, differential MAX1196-15 analog input frequency (mhz) gain (db) 2 -4 -3 -2 -1 0 1 1 10 100 1000 small-signal input bandwidth vs. analog input frequency, differential MAX1196-16 analog input frequency (mhz) gain (db) 2 -4 -3 -2 -1 0 1 v in = 100mv p-p signal-to-noise ratio vs. input power (f in = 19.88798mhz) MAX1196-17 input power (db fs) snr (db) -4 -8 -12 -16 30 35 40 45 50 55 25 -20 0 signal-to-noise + distortion vs. input power (f in = 19.88798mhz) MAX1196-18 input power (db fs) sinad (db) -4 -8 -12 -16 30 35 40 45 50 55 25 -20 0
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs _______________________________________________________________________________________ 9 typical operating characteristics (continued) (v dd = ov dd = 3v, v refin = 2.048v, differential input at -1db fs, f clk = 40mhz, c l 10pf, t a = +25 c, unless otherwise noted.) gain error vs. temperature, external reference v refin = 2.048v MAX1196-24 temperature ( c) gain error (%fs) 60 35 10 -15 0 0.1 0.2 0.3 0.4 0.5 -0.1 -40 85 cha chb total harmonic distortion vs. input power (f in = 19.88798mhz) MAX1196-19 input power (db fs) sinad (dbc) -4 -8 -12 -16 -70 -65 -60 -55 -50 -45 -75 -20 0 spurious-free dynamic range vs. input power (f in = 19.88798mhz) MAX1196-20 input power (db fs) sfdr (dbc) -4 -8 -12 -16 47 52 57 62 67 72 42 -20 0 snr/sinad, thd/sfdr vs. clock duty cycle MAX1196-21 clock duty cycle (%) snr/sinad, thd/sfdr (db, dbc) 56 52 48 44 40 50 60 70 80 30 40 60 thd sinad snr sfdr f ina/b = 7.534287mhz integral nonlinearity (131,072-point data record) MAX1196-22 digital output code inl (lsb) 224 192 128 160 64 96 32 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 256 f in = 7.534287mhz differential nonlinearity (131,072-point data record) MAX1196-23 digital output code dnl (lsb) 224 192 128 160 64 96 32 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 256 f in = 7.534287mhz offset error vs. temperature, external reference v refin = 2.048v MAX1196-25 temperature ( c) offset error (%fs) 60 35 10 -15 -0.6 -0.4 -0.2 0 0.2 -0.8 -40 85 chb cha
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs 10 ______________________________________________________________________________________ typical operating characteristics (continued) (v dd = ov dd = 3v, v refin = 2.048v, differential input at -1db fs, f clk = 40mhz, c l 10pf, t a = +25 c, unless otherwise noted.) pin description pin name function 1 com common-mode voltage input/output. bypass to gnd with a 0.1f capacitor. 2, 6, 11, 14, 15 v dd analog supply voltage. bypass to gnd with a capacitor combination of 2.2f in parallel with 0.1f. 3, 7, 10, 13, 16 gnd analog ground 4 ina+ channel a positive analog input. for single-ended operation, connect signal source to ina+. 5 ina- channel a negative analog input. for single-ended operation, connect ina- to com. 8 inb- channel b negative analog input. for single-ended operation, connect inb- to com. 9 inb+ channel b positive analog input. for single-ended operation, connect signal source to inb+. 12 clk converter clock input internal reference voltage vs. analog supply voltage MAX1196-28 v dd (v) v refout (v) 3.45 3.30 3.15 3.00 2.85 2.0304 2.0308 2.0312 2.0316 2.0320 2.0324 2.0300 2.70 3.60 internal reference voltage vs. temperature MAX1196-29 temperature ( c) v refout (v) 60 35 10 -15 2.024 2.028 2.032 2.036 2.040 2.020 -40 85 snr/sinad, thd/sfdr vs. sampling speed MAX1196-30 sampling speed (msps) snr/sinad, thd/sfdr (db, dbc) 50 40 30 20 10 -80 -60 -40 -20 0 20 40 60 80 100 -100 060 thd sinad snr sfdr f in = 20mhz analog supply current vs. temperature MAX1196-26 temperature ( c) i vdd (ma) 60 35 -15 10 26 27 28 29 30 31 32 33 25 -40 85 digital supply current vs. analog input frequency MAX1196-27 analog input frequency (mhz) i ovdd (ma) 16 12 8 4 4 5 6 7 8 3 020
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs ______________________________________________________________________________________ 11 pin description (continued) pin name function 17 t/b t/b selects the adc digital output format. high: two s complement. low: straight offset binary. 18 sleep sleep mode input. high: deactivates the two adcs, but leaves the reference bias circuit active. low: normal operation. 19 pd high-active power-down input. high: power-down mode low: normal operation 20 oe low-active output enable input. high: digital outputs disabled low: digital outputs enabled 21 29, 35, 36 n.c. no connection. do not connect. 30 a/b a/b data indicator. this digital output indicates cha data (a/b = 1) or chb data (a/b = 0) to be present on the output. a/b follows the external clock signal with typically 6ns delay. 31, 34 ognd output-driver ground 32, 33 ov dd output-driver supply voltage. bypass to ognd with a capacitor combination of 2.2f in parallel with 0.1f. 37 d0a/b three-state digital output, bit 0. depending on status of a/b, output data reflects channel a or channel b data. 38 d1a/b three-state digital output, bit 1. depending on status of a/b, output data reflects channel a or channel b data. 39 d2a/b three-state digital output, bit 2. depending on status of a/b, output data reflects channel a or channel b data. 40 d3a/b three-state digital output, bit 3. depending on status of a/b, output data reflects channel a or channel b data. 41 d4a/b three-state digital output, bit 4. depending on status of a/b, output data reflects channel a or channel b data. 42 d5a/b three-state digital output, bit 5. depending on status of a/b, output data reflects channel a or channel b data. 43 d6a/b three-state digital output, bit 6. depending on status of a/b, output data reflects channel a or channel b data. 44 d7a/b three-state digital output, bit 7 (msb). depending on status of a/b, output data reflects channel a or channel b data. 45 refout internal reference voltage output. can be connected to refin through a resistor or a resistor-divider. 46 refin reference input. v refin = 2 (v refp - v refn ). bypass to gnd with a 0.1f capacitor. 47 refp positive reference i/o. conversion range is (v refp - v refn ). bypass to gnd with a 0.1f capacitor. 48 refn negative reference i/o. conversion range is (v refp - v refn ). bypass to gnd with a 0.1f capacitor.
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs 12 ______________________________________________________________________________________ detailed description the MAX1196 uses a 7-stage, fully differential, pipelined architecture (figure 1) that allows for high-speed con- version while minimizing power consumption. samples taken at the inputs move progressively through the pipeline stages every half clock cycle. including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for cha and 5.5 clock cycles for chb. flash adcs convert the held input voltages into a digi- tal code. internal mdacs convert the digitized results back into analog voltages, which are then subtracted from the original held input signals. the resulting error signals are then multiplied by two, and the residues are passed along to the next pipeline stages where the process is repeated until the signals have been processed by all 7 stages. both input channels are sampled on the rising edge of the clock and the resulting data is multiplexed at the output. cha data is updated on the rising edge (5 clock cycles later) and chb data is updated on the falling edge (5.5 clock cycles later) of the clock signal. the a/b indicator follows the clock signal with a typical delay time of 6ns and remains high when cha data is updated and low when chb data is updated. input track-and-hold (t/h) circuits figure 2 displays a simplified functional diagram of the input track-and-hold (t/h) circuits in both track and hold mode. in track mode, switches s1, s2a, s2b, s4a, s4b, s5a, and s5b are closed. the fully differential cir- cuits sample the input signals onto the two capacitors (c2a and c2b) through switches s4a and s4b. s2a and s2b set the common mode for the amplifier input, and open simultaneously with s1, sampling the input wave- form. switches s4a, s4b, s5a, and s5b are then opened before switches s3a and s3b connect capaci- tors c1a and c1b to the output of the amplifier and switch s4c is closed. the resulting differential voltages are held on capacitors c2a and c2b. the amplifiers are used to charge capacitors c1a and c1b to the same values originally held on c2a and c2b. these values are then presented to the first stage quantizers and iso- late the pipelines from the fast-changing inputs. the wide input bandwidth t/h amplifiers allow the MAX1196 to track and sample/hold analog inputs of high frequen- cies (>nyquist). both adc inputs (ina+, inb+, ina-, and inb-) can be driven either differentially or single ended. match the impedance of ina+ and ina-, as well as inb+ and inb-, and set the common-mode voltage to midsupply (v dd /2) for optimum performance. analog inputs and reference configurations the full-scale range of the MAX1196 is determined by the internally generated voltage difference between refp (v dd /2 + v refin /4) and refn (v dd /2 - v refin /4). the full-scale range for both on-chip adcs is adjustable through the refin pin, which is provided for this purpose. 8 v ina stage 1 stage 2 digital alignment logic stage 6 stage 7 2-bit flash adc t/h 8 v inb stage 1 stage 2 digital alignment logic stage 6 stage 7 2-bit flash adc t/h output multiplexer 8 d0a/b?7a/b figure 1. pipelined architecture?tage blocks
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs ______________________________________________________________________________________ 13 the MAX1196 provides three modes of reference operation: internal reference mode buffered external reference mode unbuffered external reference mode in internal reference mode, connect the internal refer- ence output refout to refin through a resistor (e.g., 10k ? ) or resistor-divider, if an application requires a reduced full-scale range. for stability and noise-filtering purposes, bypass refin with a 0.1f capacitor to gnd. in internal reference mode, refout, com, refp, and refn become low-impedance outputs. in buffered external reference mode, adjust the refer- ence voltage levels externally by applying a stable and accurate voltage at refin. in this mode, com, refp, s3b s3a com s5b s5a inb+ inb- s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com hold hold clk internal nonoverlapping clock signals track track s2a s2b s3b s3a com s5b s5a ina+ ina- s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com s2a s2b MAX1196 figure 2. MAX1196 t/h amplifiers
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs 14 ______________________________________________________________________________________ t dob t cl t ch t clk t doa t da/b 5 clock-cycle latency (cha), 5.5 clock-cycle latency (chb) a/b chb d0a/b d7a/b d0b cha d1a chb d1b cha d2a chb d2b cha d3a chb d3b cha d4a chb d4b cha d5a chb d5b cha d6a chb d6b cha chb clk figure 3. system timing diagram and refn are outputs. refout can be left open or connected to refin through a >10k ? resistor. in unbuffered external reference mode, connect refin to gnd. this deactivates the on-chip reference buffers for refp, com, and refn. with their buffers shut down, these nodes become high-impedance inputs and can be driven through separate, external reference sources. for detailed circuit suggestions and how to drive this dual adc in buffered/unbuffered external reference mode, see the applications information section. clock input (clk) the MAX1196 s clk input accepts cmos-compatible clock signal. since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). in particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. any significant aperture jitter would limit the snr perfor- mance of the on-chip adcs as follows: where f in represents the analog input frequency and t aj is the time of the aperture jitter. clock jitter is especially critical for undersampling applications. the clock input should always be consid- ered as an analog input and routed away from any ana- log input or other digital signal lines. the MAX1196 clock input operates with a voltage threshold set to v dd /2. clock inputs with a duty cycle other than 50%, must meet the specifications for high and low periods as stated in the electrical characteristics. system timing requirements figure 3 shows the relationship between clock and analog input, a/b indicator, and the resulting valid cha/chb data output. cha and chb data are sam- pled on the rising edge of the clock signal. following the rising edge of the 5th clock cycles, the digitized value of the original cha sample is presented at the output, followed one-half clock cycle later by the digi- tized value of the original chb sample. a channel selection signal (a/b indicator) allows the user to determine which output data represents which input channel. with a/b = 1, digitized data from cha is present at the output and with a/b = 0 digitized data from chb is present. snr ft in aj log = ? ? ? ? ? ? 20 1 2
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs ______________________________________________________________________________________ 15 digital output data, output data format selection (t/b), output enable ( oe ), channel selection (a/b) all digital outputs, d0a/b d7a/b (cha or chb data) and a/b are ttl/cmos-logic compatible. the output coding can be chosen to be either offset binary or two s comple- ment (table 1) controlled by a single pin (t/b). pull t/b low to select offset binary and high to activate two s com- plement output coding. the capacitive load on the digital outputs d0a/b d7a/b should be kept as low as possible (<15pf), to avoid large digital currents that could feed back into the analog portion of the MAX1196, thereby degrading its dynamic performance. using buffers on the digital outputs of the adcs can further isolate the digital outputs from heavy capacitive loads. to further improve the dynamic performance of the MAX1196, small-series resistors (e.g., 100 ? ) can be added to the digital output paths, close to the MAX1196. figure 4 displays the timing relationship between out- put enable and data output valid as well as power- down/wake-up and data output valid. power-down (pd) and sleep (sleep) modes the MAX1196 offers two power-save modes sleep and full power-down mode. in sleep mode (sleep = 1), only the reference bias circuit is active (both adcs are disabled), and current consumption is reduced to 3ma. to enter full power-down mode, pull pd high. with oe simultaneously low, all outputs are latched at the last value prior to the power down. pulling oe high forces the digital outputs into a high-impedance state. applications information figure 5 depicts a typical application circuit containing two single-ended-to-differential converters. the internal reference provides a v dd /2 output voltage for level-shift- ing purposes. the input is buffered and then split to a voltage follower and inverter. one lowpass filter per amplifier suppresses some of the wideband noise asso- ciated with high-speed operational amplifiers. the user can select the r iso and c in values to optimize the filter performance, to suit a particular application. for the application in figure 5, an r iso of 50 ? is placed before the capacitive load to prevent ringing and oscillation. the 22pf c in capacitor acts as a small filter capacitor. using transformer coupling an rf transformer (figure 6) provides an excellent solu- tion to convert a single-ended source signal to a fully dif- ferential signal, required by the MAX1196 for optimum performance. connecting the center tap of the trans- former to com provides a v dd /2 dc level shift to the input. although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive require- ments. a reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. differential input voltage* differential input straight offset binary t/b = 0 two s complement t/b = 1 v ref 255/256 +full scale - 1lsb 1111 1111 0111 1111 v ref 1/256 +1lsb 1000 0001 0000 0001 0 bipolar zero 1000 0000 0000 0000 -v ref 1/256 -1lsb 0111 1111 1111 1111 -v ref 255/256 -full scale + 1lsb 0000 0001 1000 0001 -v ref 256/256 -full scale 0000 0000 1000 0000 table 1. MAX1196 output codes for differential inputs * v ref = v refp - v refn output d0a/b d7a/b oe t disable t enable high-z high-z valid data figure 4. output timing diagram
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs 16 ______________________________________________________________________________________ input 300 ? -5v +5v 0.1 f 0.1 f 0.1 f -5v 600 ? 300 ? 300 ? ina- ina+ lowpass filter com 600 ? +5v -5v 0.1 f 600 ? 300 ? 600 ? 300 ? 0.1 f 0.1 f 0.1 f +5v 0.1 f 300 ? max4108 MAX1196 inb- inb+ max4108 max4108 lowpass filter input 300 ? -5v +5v 0.1 f 0.1 f 0.1 f c in 22pf -5v 600 ? 300 ? 300 ? lowpass filter 600 ? +5v -5v 0.1 f 600 ? 300 ? 600 ? 300 ? 0.1 f 0.1 f 0.1 f +5v 0.1 f 300 ? max4108 max4108 max4108 300 ? lowpass filter r is0 50 ? c in 22pf r is0 50 ? c in 22pf r is0 50 ? c in 22pf r is0 50 ? figure 5. typical application for single-ended-to-differential conversion
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs ______________________________________________________________________________________ 17 in general, the MAX1196 provides better sfdr and thd with fully differential input signals than single- ended drive, especially for very high input frequencies. in differential input mode, even-order harmonics are lower as both inputs (ina+, ina- and/or inb+, inb-) are balanced, and each of the adc inputs only requires half the signal swing compared to single-ended mode. single-ended ac-coupled input signal figure 7 shows an ac-coupled, single-ended applica- tion. amplifiers like the max4108 provide high speed, high bandwidth, low noise, and low distortion to main- tain the integrity of the input signal. buffered external reference drives multiple adcs multiple-converter systems based on the MAX1196 are well suited for use with a common reference voltage. the refin pin of those converters can be connected directly to an external reference source. a precision bandgap reference like the max6062 gen- erates an external dc level of 2.048v (figure 8), and exhibits a noise voltage density of 150nv/ hz . its out- put passes through a one-pole lowpass filter (with 10hz cutoff frequency) to the max4250, which buffers the reference before its output is applied to a second 10hz lowpass filter. the max4250 provides a low offset volt- age (for high gain accuracy) and a low noise level. the passive 10hz filter following the buffer attenuates noise MAX1196 t1 n.c. v in 6 1 5 2 4 3 22pf 22pf 0.1 f 0.1 f 2.2 f 25 ? 25 ? minicircuits tt1-6-kk81 t1 n.c. v in 6 1 5 2 4 3 22pf 22pf 0.1 f 0.1 f 2.2 f 25 ? 25 ? minicircuits tt1-6-kk81 ina- ina+ inb- inb+ com figure 6. transformer-coupled input drive MAX1196 0.1 f 1k ? 1k ? 100 ? 100 ? c in 22pf c in 22pf inb+ inb- com ina+ ina- 0.1 f r iso 50 ? r iso 50 ? refp refn v in max4108 0.1 f 1k ? 1k ? 100 ? 100 ? c in 22pf c in 22pf 0.1 f r iso 50 ? r iso 50 ? refp refn v in max4108 figure 7. using an op amp for single-ended, ac-coupled input drive
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs 18 ______________________________________________________________________________________ produced in the voltage-reference and buffer stages. this filtered noise density, which decreases for higher frequencies, meets the noise levels specified for preci- sion-adc operation. unbuffered external reference drives multiple adcs connecting each refin to analog ground disables the internal reference of each device, allowing the internal reference ladders to be driven directly by a set of exter- nal reference sources. followed by a 10hz lowpass fil- ter and precision voltage-divider, the max6066 generates a dc level of 2.500v. the buffered outputs of this divider are set to 2.0v, 1.5v, and 1.0v, with an accuracy that depends on the tolerance of the divider resistors. those three voltages are buffered by the max4252, which provides low noise and low dc offset. the individ- ual voltage followers are connected to 10hz lowpass fil- ters, which filter both the reference-voltage and amplifier noise to a level of 3nv/ hz . the 2.0v and 1.0v reference voltages set the differential full-scale range of the asso- ciated adcs at 2v p-p . the 2.0v and 1.0v buffers drive the adcs internal ladder resistances between them. note that the common power supply for all active com- ponents removes any concern regarding power-supply sequencing when powering up or down. with the outputs of the max4252 matching better than 0.1%, the buffers and subsequent lowpass filters can be replicated to support as many as 32 adcs. for applications requiring more than 32 matched adcs, a voltage-reference and divider string common to all con- verters is highly recommended. max4250 max6062 16.2k ? 162 ? 3.3v 2 4 2 3 5 10hz lowpass filter 10hz lowpass filter 1 1 refout refp refin 1 f MAX1196 n = 1 refn 29 n.c. 2.048v n.c. 31 32 1 2 29 31 32 1 2 com refout note: one front-end reference circuit design can be used with up to 1000 adcs. refp refin MAX1196 n = 1000 refn com 3 0.1 f 0.1 f 3.3v 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 2.2 f 10v 0.1 f 0.1 f 0.1 f 100 f 0.1 f figure 8. external buffered (max4250) reference drive using a max6062 bandgap reference
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs ______________________________________________________________________________________ 19 typical qam demodulation application a frequently used modulation technique in digital com- munications applications is quadrature amplitude mod- ulation (qam). typically found in spread- spectrum- based systems, a qam signal represents a carrier fre- quency modulated in both amplitude and phase. at the transmitter, modulating the baseband signal with quad- rature outputs, a local oscillator followed by subse- quent up-conversion can generate the qam signal. the result is an in-phase (i) and a quadrature (q) carrier component, where the q component is 90 degrees phase-shifted with respect to the in-phase component. at the receiver, the qam signal is divided down into its i and q components, essentially representing the mod- ulation process reversed. figure 10 displays the demodulation process performed in the analog domain, using the dual matched 3v, 8-bit adc MAX1196, and the max2451 quadrature demodulator to recover and digitize the i and q baseband signals. before being digitized by the MAX1196, the mixed-down signal com- ponents can be filtered by matched analog filters, such 1/4 max4252 max6066 1/4 max4252 1/4 max4252 1.47k ? 21.5k ? 21.5k ? 21.5k ? 21.5k ? 21.5k ? 47k ? 3.3v 3.3v 11 2 2 3 4 1 1 refout refp refin 1 f 10 f 6v MAX1196 n = 1 refn 29 n.c. n.c. 31 32 1 2 29 31 32 1 2 com refout note: one front-end reference circuit design can be used with up to 32 adcs. refp refin MAX1196 n = 32 refn com 2.0v at 8ma 3 0.1 f 0.1 f max4254 power-supply bypassing. place capacitor as close as possible to the op amp. 3.3v 1.47k ? 47k ? 3.3v 1.5v 11 6 5 4 7 10 f 6v 1.5v at 0ma 1.47k ? 47k ? 3.3v 11 9 10 4 8 10 f 6v 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 2.2 f 10v 0.1 f 0.1 f 1.0v at -8ma 330 f 6v 330 f 6v 330 f 6v 2.0v 1.0v figure 9. external unbuffered reference drive with max4252 and max6066
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs 20 ______________________________________________________________________________________ as nyquist or pulse-shaping filters, which remove unwanted images from the mixing process, thereby enhancing the overall signal-to-noise (snr) perfor- mance and minimizing intersymbol interference. grounding, bypassing, and board layout the MAX1196 requires high-speed board layout design techniques. locate all bypass capacitors as close to the device as possible, preferably on the same side as the adc, using surface-mount devices for minimum inductance. bypass v dd , refp, refn, and com with two parallel 0.1f ceramic capacitors and a 2.2f bipolar capacitor to gnd. follow the same rules to bypass the digital supply (ov dd ) to ognd. multilayer boards with separated ground and power planes pro- duce the highest level of signal integrity. consider the use of a split ground plane arranged to match the physical location of the analog ground (gnd) and the digital output-driver ground (ognd) on the adc s package. the two ground planes should be joined at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. the ideal location of this connection can be determined experi- mentally at a point along the gap between the two ground planes, which produces optimum results. make this connection with a low-value, surface-mount resistor (1 ? to 5 ? ), a ferrite bead, or a direct short. alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or dsp ground plane). route high-speed digital signal traces away from the sensitive analog traces of either channel. make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. keep all signal lines short and free of 90 degree turns. static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. the static lin- earity parameters for the MAX1196 are measured using the best-straight-line fit method. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. dynamic parameter definitions aperture jitter figure 11 depicts the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (figure 11). 0 90 8 downconverter max2451 ina+ MAX1196 ina- inb+ inb- dsp post- processing a/b cha and chb data alternatingly available on 8-bit multiplexed output bus. figure 10. typical qam application using the MAX1196
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs ______________________________________________________________________________________ 21 signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc s reso- lution (n bits): snr db[max] = 6.02 db n + 1.76 db in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five har- monics, and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to all spectral components minus the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adc error consists of quantization noise only. enob for a full-scale sinusoidal input waveform is computed from: total harmonic distortion (thd) thd is typically the ratio of the rms sum of the first four harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next largest spurious component, excluding dc offset. intermodulation distortion (imd) the two-tone imd is the ratio expressed in decibels of either input tone to the worst third-order (or higher) intermodulation products. the individual input tone lev- els are at -7db full scale. pin-compatible upgrades (sampling speed and resolution) chip information transistor count: 11,601 process: cmos thd vv v v v log = ++ ? ? ? ? ? ? ? ? + 20 2 2 3 2 4 2 5 2 1 enob sinad = ? ? ? ? ? ? - 1.76 6.02 hold analog input sampled data (t/h) t/h t ad t aj track track clk figure 11. t/h aperture timing 8-bit part 10-bit part sampling speed (msps) n/a max1185 20 max1195 max1183 40 max1197 max1182 60 max1198 max1180 100 n/a max1190 120 MAX1196 max1186 40, multiplexed
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs 22 ______________________________________________________________________________________ gnd reference output drivers control t/h t/h adc dec mux refout refn com refp refin ina+ ina- clk inb+ inb- v dd dec adc ognd ov dd a/b oe d7b d0b or d7a d0a t/b pd sleep MAX1196 8 8 8 8 functional diagram
MAX1196 dual 8-bit, 40msps, 3v, low-power adc with internal reference and multiplexed parallel outputs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 23 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 48l,tqfp.eps

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